Symposium "A new era for high-level synthesis"

1 December 2010, 13:30 – 19:00

Het Pand, Onderbergen 1, 9000 Gent, Belgium

In cooperation with IEEE Embedded Systems Benelux Chapter and IEEE Circuits and Systems Benelux Chapter

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Abstracts and bio’s

Dirk Stroobandt

Bio

Dirk Stroobandt is professor at Ghent University, affiliated with the Department of Electronics and Information Systems (ELIS), Computer Systems Lab (CSL). He currently leads the research group HES (Hardware and Embedded Systems) of about 10 people with interests in semi-automatic hardware design methodologies and tools, parameterizable run-time FPGA reconfiguration and reconfigurable multiprocessor networks. He is also the project leader of the FlexWare project.
Dirk Stroobandt is the inaugural winner of the ACM/SIGDA Outstanding Doctoral Thesis Award in Design Automation (1999) and also received the `Scientific prize Alcatel Bell' in 2002.
Dirk Stroobandt has been visiting researcher at the University of California at Irvine (April to July 1997) and at the Computer Science Department of the University of California at Los Angeles (UCLA) (July 1999 to June 2000). He initiated and co-organized the International Workshop on System-Level Interconnect Prediction (SLIP) in 1999 and was guest editor of two special issues of the IEEE Transactions on VLSI Systems on System-Level Interconnect Prediction and a special issue on SLIP for Integration, the VLSI Journal. He has been associate editor of ACM's TODAES.

Abstract: "The FlexWare project in a new era for high-level synthesis"

This symposium marks the completion of the FlexWare project, an IWT sponsored SBO project, targeting hardware acceleration of massively parallel applications by exploiting flexible parallel hardware platforms. The project enables the efficient design of hardware accelerators for algorithms with massive, low-level parallelism, organised in a regular loop structure. Applications from various domains fit this description, e.g., video and image processing, finite element simulation, medical imaging and diagnosis, vision based analysis of product quality, speech processing, ...
The symposium will address new evolutions in high-level synthesis in a broader context, with presentations on automation of high-level synthesis, tools for high-level synthesis, new computing architectures and ways to efficiently compile applications into these architectures.

Paolo Ienne

Bio

Paolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, from 1990 to 1991, he was an undergraduate researcher with Brunel University, Uxbridge, U.K. From 1992 to 1996, he was a Research Assistant at the Microcomputing Laboratory (LAMI) and at the MANTRA Center for Neuro-Mimetic Systems of the EPFL. In December 1996, he joined the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG). After working on datapath generation tools, he became Head of the embedded memory unit in the Design Libraries division.
His research interests include various aspects of computer and processor architecture, electronic design automation, computer arithmetic, reconfigurable computing, and multiprocessor systems-on-chip.
Dr. Ienne was a recipient of Best Paper Award at the 40th Design Automation Conference (DAC) in 2003, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES) in 2007, and at the 19th International Conference on Field-Programmable Logic and Applications (FPL) in 2009. In 2008, he has been General Co-Chair of the 6th IEEE Symposium on Application Specific Processors (SASP) and Guest Editor of a Special Section on Application Specific Processors which appeared in October 2008 on the IEEE Transactions on Very Large Scale Integration Systems. In 2010, he has been the Program Subcommittee Chair of the Design Automation Conference (DAC) on High-Level and Logic Synthesis. In 2010 and 2011, he is a Topic Co-Chair of Design Automation and Test in Europe (DATE) for Architectural and High-Level Synthesis topic. In 2011, he will be a Program Co-Chair of the 20th IEEE Symposium on Computer Arithmetic (ARITH) and a Program Co-Chair of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). He is or has been a member of some fifty program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design.

Abstract: The Irresistible Charm of Automation

For decades, researchers in computer arithmetic have explored empirically the available design space and have identified through their intuition some incredibly cunning solutions which have progressively enriched the tools of the trade of the designers. With complexity growing exponentially and short design time becoming increasingly critical to market dominance, it is high time to begin automating the design process at these relatively high levels of abstraction. Despite the impressive progress of logic synthesis in the past decades, finding the best architecture for a given circuit still remains an open problem and largely unsolved. In most arithmetic circuits, the outcome of the synthesis tools depends on the input description of the circuit. In other words, logic synthesis optimizations hardly change the architecture of the given circuit. Achieving useful results in the synthesis of arithmetic components is far from trivial because the space of possible solutions is enormous, often the problem constraints are ill defined or complex to capture, human intuition is incredibly powerful to cope with such broad constraints, and more than half a century of human research is hard to challenge using only dumb computers. Nevertheless, the temptation for design automation to penetrate these classically empirical domains is irresistible and some tangible advances are possible: even reproducing some results known in literature, fully automatically and without embedding any prior knowledge, is a significant achievement. And, occasionally, automation can lead to unexpected rewards.

Jason Villarreal

Bio

Jason Villarreal is a senior engineer at Jacquard Computing, Inc. and is the lead designer of the ROCCC 2.0 framework. His research interests include high and low level compiler optimizations for hardware generation. He received his B.S. and Ph.D in computer science from the University of California, Riverside in 1998 and 2008 respectively.

Abstract: "Design Challenges in the Development of the Riverside Optimizing Compiler for Configurable Computing"

ROCCC 2.0 (Riverside Optimizing Compiler for Configurable Computing) is a C to VHDL compilation framework specifically focused on FPGA-based code acceleration. Unlike similar tools designed for high-level synthesis, ROCCC does not support the generation of arbitrary hardware circuits but instead focuses on compile time transformations and optimizations aimed at generating efficient hardware accelerator circuits from a loop nest in C. Novel features of ROCCC include intuitive modular bottom-up design of circuits completely specified in C, the separation of code generation from FPGA platform specifics, and extensive control of optimizations including specific hardware optimizations such as systolic array generation and triple modular redundancy. The control of optimizations and modular approach to circuit construction enables tuning generated circuits to maximize parallelism, minimize cycle time, and minimize area used within the constraints of a target device while also allowing for design space exploration from a single C description. Additionally, ROCCC contains a framework that supports the integration of external IP in the form of VHDL or netlists into generated circuits. ROCCC has been ported to several platforms, including Xilinx development boards, the Pico Computing platforms, and the Convey Computers HC-1. In this talk I will discuss the design challenges and decisions involved in the development of ROCCC 2.0 as well as current results and future challenges.

Paul Stravers

Bio

Paul Stravers has roots deep in NXP and Philips, with focus on platforms for digital media processing, processors, and hardware/software co-design.
He led the CAKE/Wasabi project in the research phase, developing a low-cost, high-powered programmable multi-processor architecture, and then contributed to its transformation into production-quality technology. His processor research and design have resulted in a series of first-time right silicon implementations of the MIPS architecture that are widely deployed in NXP systems-on-chip. Paul Stravers holds a PhD and a cum laude master’s degree in electrical engineering from Delft University of Technology.

Paul has filed 11 US patents.

Abstract: Need parallel programs? Think sequential!

Parallel hardware is cheap and abundant these days, but programming has proved a hard problem. The human mind is poorly equipped to oversee the behavior of a program with many task interleavings; and high-level parallel languages tend to be effective only in specific application domains.
In this presentation we propose a general purpose source-to-source compilation flow that enables programmers to interactively explore parallelization opportunities of a sequential C program. The sequential program structure and behavior is presented on an innovative graphical display, enabling programmers to quickly grasp the program's hot spots and data dependencies. Critical code sections can be parallelized and mapped to a range of compute resources, including symmetric multiprocessors, GPUs and FPGA accelerators. The resulting C program can contain a mix of parallel implementation paradigms, including POSIX threads and OpenCL.
Data dependencies in the program sometimes prevent parallelization of critical loops or limit attainable speedups. The proposed flow includes detailed dependency analysis to direct the programmer's attention to problematic data structures in his sequential program. As a result the programmer can fix his sequential code such that it is amenable to higher speedups.
Traditional source-to-source tools produce machine-generated C-code that vastly differs from the original program and is therefore not suited to serve as reference for further refinement into hardware functions or optimized DSP code. The proposed compilation flow promotes full ownership of the resulting parallel source code in terms of readability and maintainability by providing the source modifications as incremental refactoring recipes that can be applied to the original program either manually or automatically.
The proposed source-to-source flow is released as part of vfAnalyst, a commercially supported design tool targeting embedded system creators.

Nigel Topham

Bio

Nigel Topham is Professor of Computer Systems at The University of Edinburgh, and was a founding director of the Institute for Computing Systems Architecture, wcms.inf.ed.ac.uk/icsa at Edinburgh. Prof. Topham has held a number of senior positions in the semiconductor intellectual property industry. He was previously a CTO for ARC International and also their Chief Architect. At ARC he led the design of the low-power ARC 600 processor, which today powers around 60% of all flash memory products sold worldwide. Prior to that he was co-founder of a UK semiconductor startup company, later acquired by a major FPGA company.

He currently leads a research group that is innovating in new methods of creating low-power microprocessors for mobile and embedded computing systems, and their related software tools. A key strand of this research is to find fast methods of searching the complex design space of embedded microprocessors with automated instruction-set extensions.

Professor Topham was elected a Fellow of the Royal Academy of Engineering in 2008.

Abstract: "The Inevitable Complexity of Customization"

When a microprocessor is automatically extended through the introduction of new application-specific instructions, we see an explosion in the space of possible designs. In addition to the choice of selecting the most appropriate subset of possible extension instructions, there is also the highly complex choice of how to merge, or combine, their logical implementations in order to optimize the objective functions of speed, area and power consumption.

This talk looks at the approach taken in the PASTA project at Edinburgh to enumerate this design space, to search it, and to devise machine-learning methods that will find good solutions quickly and accurately.

Steven Teig, President and CTO, Tabula, Inc.

Bio

Steve Teig is the President and CTO of Tabula and the inventor of Tabula’s Spacetime 3-Dimensional Programmable Logic Architecture. Prior to co-founding Tabula, Steve was co-CTO of Cadence (NSDQ:CDNS). Steve joined Cadence through its acquisition of Simplex (NSDQ: SPLX), where he was also CTO. At Simplex, Steve invented and led the technology development for the X Architecture, which radically improves chip design by pervasively incorporating diagonal wiring. Before joining Simplex, Steve co-founded two successful biotechnology companies: CombiChem (NSDQ: CCHM, later acquired by DuPont Pharmaceuticals), where he was CTO, and BioCAD, where he was CTO and, later, CEO. At CombiChem, Steve invented and led the development of the company’s revolutionary Discovery Engine technology, with which CombiChem discovered pharmaceutical-lead compounds for 11 different therapeutic areas in only five years. At BioCAD, Steve led the design of Catalyst, which was the first widely used, pharmaceutical discovery software and is still a leading software package used worldwide.

In the 1980s, Steve spent several years in the EDA industry, where his work had a major impact still felt today. First, at Trilogy Systems in 1982, he invented compiled-code logic simulation and led the development of the first simulator based on that technology. Then, as CTO and co-founder of Tangent Systems in 1984 (which later became Cadence’s very first acquisition), he invented the principal place-and-route algorithms for the Tancell and Tangate products. Tancell was the first commercial, timing-driven P&R system and the first product to use analytical placement, among other distinctions. Tangate, which was the first commercial, sea-of-gates P&R system, became Cadence’s Gate Ensemble and Cell-3 Ensemble products, which have cumulatively generated over $2 B in revenue.

Steve received a B.S.E. in Electrical Engineering and Computer Science from Princeton University. He holds over 225 patents. In 2002, he broke Thomas Edison’s record for the number of patents filed by an individual in a single year.

Abstract: "Spacetime: a programmable fabric beyond the FPGA"

Programmable fabrics, such as FPGAs, have existed since at least 1984, but commercial FPGA architectures have stagnated over the last decade, leaving today’s FPGAs with the same 20-50x price/performance disadvantage vs. ASICs that they had 10 years ago. Spacetime is a new approach to constructing a programmable fabric, based on novel, ultra-high-performance, sub-ns-reconfigurable hardware coupled with an easily grasped metaphor that completely hides the underlying, on-the-fly reconfiguration, thus facilitating the automated mapping of computations to the fabric. While the idea of reconfiguration is not new, dating back to Turing or even earlier, the representation of the temporal aspects of computing in a spatial way, as Special Relativity does for physics, is new, and Minkowski’s space-time geometry concisely encapsulates key requirements for the correctness and performance of computations mapped to MIMD fabrics, such as FPGAs, multi-core microprocessors, and Tabula’s 3PLDs. As such, our embodiment of these ideas in Spacetime offers not only a 5x price/performance advantage vs. FPGA but also vital aspects of the compiler technology that will be required for multi-core and other multi-computing hardware implementations.