The FlexWare project
The FlexWare project has been running from 1/1/2007 to 31/12/2010 as an IWT sponsored SBO project, targeting hardware acceleration of massively parallel applications by exploiting flexible parallel hardware platforms.
The project wants to enable the efficient design of hardware accelerators for algorithms with massive, low-level parallelism, organised in a regular loop structure. Applications from various domains fit this description, e.g., video and image processing, finite element simulation, medical imaging and diagnosis, vision based analysis of product quality, speech processing, ... The primary application domain targeted in the FlexWare project is that of computation intensive bioinformatics applications.
To realise cost-effective accelerators, we propose to use flexible, parallel hardware platforms, i.e., platforms that are retargetable, by platform reconfiguration or by executable code generation, and offer sufficient low-level data path and memory parallelism. Today, a range of hardware platforms with different types and degrees of parallelism exist or are being developed. When faced with a new application, it is far from obvious which platform would offer the best cost-performance. To drastically reduce the R&D cost of accelerating new algorithms, we will develop new methods and tools for guiding the discrimination between alternative platforms, as well as for automatically extracting application parallelism and optimally mapping it to the resources offered by several specific hardware platforms. The proposed research will also result in cost-effective accelerators for bioinformatics applications as well as accelerator prototypes for several other applications from diverse application domains.
To achieve a good understanding of the relative strengths and weaknesses of different types of hardware platforms, we will explore and compare the acceleration potential and cost- performance offered by a range of four flexible, parallel computing platforms: FPGA, ADRES , FEENECS and DSP. Together, they cover a range of degrees of flexibility and different types of parallelism. To enable the efficient exploitation of the FPGA, ADRES and FEENECS platforms, the FlexWare project consortium will address the problem of automatic extraction of application parallelism as a common first step to automated design. The results will be used to develop or improve compilers (ADRES and FEENECS) or design tools (FPGA). Parts of the developed tools will be used to predict the performance of the different FlexWare platforms when accelerating new applications. The generic nature of the resulting tools will be demonstrated by applying them to algorithms from other application domains.